1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device including multiple insulating films alternately stacked with multiple electrode films and a method for manufacturing the same.
2. Background Art
Semiconductor memory devices of flash memory and the like conventionally are constructed by two-dimensionally integrating memory cells on the surface of a silicon substrate. In such a semiconductor memory device, it is necessary to increase the integration of memory cells to reduce the cost per bit and increase the storage capacity. However, such high integration in recent years has become difficult in regard to both cost and technology.
Methods of three-dimensional integration by stacking memory cells have been proposed as technology to breakthrough the limitations of increasing the integration. However, methods that simply stack and pattern one layer after another undesirably increase the number of steps as the number of stacks increases, and the costs undesirably increase. In particular, the increase of lithography steps for patterning the transistor structure is a main cause of increasing costs. Therefore, the reduction of the chip surface area per bit by stacking has not led to lower costs per bit as much as downsizing within the chip plane and is problematic as a method for increasing the storage capacity.
In consideration of such problems, the inventors have proposed a collectively patterned three-dimensional stacked memory (for example, refer to JP-A 2007-266143 (Kokai)). In such technology, selection transistors including silicon pillars aligned in the vertical direction as channels are formed on a silicon substrate and a stacked body is formed thereupon by alternately stacking electrode films and insulative films and subsequently making through-holes in the stacked body by collective patterning. A charge storage layer is formed on a side face of each through-hole, and silicon pillars are newly buried in the interiors of through-holes to connect to the silicon pillars of the selection transistors. A memory transistor is thereby formed at an intersection between each electrode film and the silicon pillar. Then, selection transistors are further formed thereupon.
In such a collectively patterned three-dimensional stacked memory, a charge can be removed from and put into the charge storage layer from the silicon pillar to store information by controlling an electrical potential of each electrode film and each silicon pillar. According to such technology, the through-holes are made by collectively patterning the stacked body. Therefore, the number of lithography steps does not increase and cost increases can be suppressed even in the case where the number of stacks of the electrode films increases.
However, to construct such a collectively patterned three dimensional stacked memory, it is necessary to remove silicon oxide of native oxide films and the like from the bottom faces of the through-holes when burying silicon pillars in the interiors of the through-holes made in the stacked body to provide good electrical contact between the silicon pillars forming the channels of the selection transistors and the newly buried silicon pillars. Normally, pre-processing is performed using a hydrofluoric acid-based solution prior to burying the silicon pillars in the through-holes. However, such pre-processing damages the charge storage layer and undesirably causes deterioration of the memory transistor characteristics.